Processor architecture and performance

Give each component a precise job

Real processors may have many general-purpose registers rather than one accumulator. The diagram uses the simplified accumulator model for the worked trace.

An instruction contains an operation and, where needed, an operand. For a direct-address load, the operand identifies a memory location whose contents are required. The control unit decodes the operation, issues control signals and coordinates transfers.

The ALU can add, subtract, compare and perform operations such as AND. A comparison may affect status flags used by a later conditional branch.

Connect the fetch cycle to an assembly instruction

In a typical school model, PC is copied to MAR; the control unit requests a memory read; the instruction travels into MDR and then CIR; PC advances to the next instruction.

Exact physical timing varies, so state the model instead of claiming every processor copies registers in an identical order.

For LDA 20, fetching obtains the instruction first. Executing it requires a second memory access: MAR becomes 20, MDR receives the contents of location 20, then ACC receives that value.

For ADD 21, location 21 supplies an operand to the ALU, which adds it to ACC. A branch replaces the next-instruction address in PC. Do not put an operand's value into MAR when an address is required.

Clock frequency: cycles per second

A higher clock frequency offers more cycles per second. If an otherwise identical CPU executes the same number of cycles without additional delays, it finishes sooner. Different instruction sets, instructions per cycle, thermal limits and memory waits make clock-only comparisons unreliable between different processors.

Raising frequency can increase power consumption and heat.

Cache: reduce repeated memory waits

Cache holds copies of recently or frequently used instructions/data close to the processor. A cache hit can avoid a slower main-memory access; a miss still requires lower-level memory.

Larger cache may improve a program that repeatedly reuses a working set, but gives little benefit to some streaming workloads. Cache is distinct from registers and from the disk that stores files.

Cores: identify independent work

Several cores can run different processes or parallel parts of one process. If the next calculation depends on the previous result, additional cores cannot simply divide that sequence evenly. Communication, synchronisation and shared-memory contention reduce ideal speed-up. Identify the independent work before recommending more cores.

Pipelining overlaps stages

In a three-stage model, one instruction is fetched while an earlier one is decoded and an earlier one is executed. The pipeline increases throughput after filling; it does not reduce the three-stage latency of one instruction.

A data dependency may require a stall, and a branch can invalidate instructions fetched along the wrong path. Filling, draining and hazards explain why the ideal rate is not always achieved.

Compare memory architectures

Von Neumann architecture uses a shared memory/address space for instructions and data, with a shared transfer path in the simple model. An instruction fetch and data transfer compete for that path.

Harvard architecture separates instruction and data memories and their buses, allowing suitable instruction/data accesses concurrently. Separate stores can also need different widths or capacities.

Contemporary processors often combine ideas: separate instruction/data caches near a core, unified main memory further away, multiple execution units and several cores. This is often called a modified Harvard arrangement.

Describe the actual separation in the scenario; do not infer that every modern CPU is purely one historical architecture.

Original A-Level practice

4 original questions total 15 marks. Attempt each before opening the independently written indicative marking guidance.