Interrupts let the processor respond to events; scheduling decides which ready process gets CPU time. Keep the event-handling mechanism separate from the policy used to choose the next process.
Content owner: Michael Print · Written for A-Level learners · Checked against official specifications
The idea to start with
An interrupt requests attention because an event occurred, such as I/O completion or a timer expiry. The processor saves sufficient state, executes the appropriate interrupt service routine (ISR), then restores state so execution can continue correctly.
A scheduler chooses among ready processes. FCFS follows arrival order; round robin rotates time slices; SJF selects a shortest next burst without preemption; SRT can preempt for a shorter remaining burst; feedback queues adjust priorities using observed behaviour.
OCR H446 · 1.2.1(c–d)
Before you start
Useful foundations
Fetch–decode–execute and PC/register roles
Processes, CPU bursts and queues
By the end, you should be able to
Explain saving and restoring processor context for an ISR
Trace FCFS, round robin, SJF, SRT and multilevel feedback queues
Calculate completion, turnaround, waiting and response times
Evaluate responsiveness, overhead and starvation
Interrupts in the fetch–decode–execute model
Repeatedly checking a device is polling and can waste CPU time. With interrupts, a device can signal that input is ready or output has completed. A timer interrupt gives the OS an opportunity to regain control and implement preemptive time slicing.
Hardware events are not the only possible sources: software can also request privileged services or raise exceptions, depending on the machine's conventions.
In the school model, the CPU checks pending enabled interrupts after completing an instruction. Priorities and masking may defer one or allow a higher-priority interrupt to interrupt an ISR.
An interrupt does not necessarily switch processes. The CPU can service it and resume the same process.
Accept, handle, then resume
1
Save context
Save the return PC and required registers/status so the current process can resume correctly.
2
Select the ISR
Identify the interrupt source and transfer control to its interrupt service routine.
3
Handle the event
Execute the ISR and acknowledge/handle the event.
4
Restore and return
Restore the saved context, then return to the correct continuation point.
Define the quantities before drawing a timeline
A ready process can run but is waiting for a CPU; a blocked process waits for an event such as I/O completion. Do not schedule a blocked process just because its priority is high.
A CPU burst is an interval of processing before termination or blocking. Our examples have one burst per job and ignore context-switch overhead.
Turnaround = completion − arrival. Waiting = turnaround − CPU burst, in this one-burst/no-I/O model. Response = first start − arrival. A process can receive a quick first response but finish much later.
A preemptive scheduler can stop a running process before its burst finishes; a non-preemptive scheduler lets it run until it blocks or finishes.
FCFS and round robin
First come first served (FCFS) takes ready jobs in arrival order. It is simple and incurs few switches, but a long burst delays short jobs behind it: the convoy effect. In the non-preemptive model, a later arrival cannot displace the running job.
Round robin gives each ready process up to a quantum of CPU time, then returns an unfinished job to the queue's end. A smaller quantum improves opportunities for interaction but increases switching overhead. A very large quantum approaches FCFS.
Specify how arrivals at a slice boundary are ordered; otherwise two defensible traces may differ.
Shortest job first and shortest remaining time
Shortest job first (SJF) selects the shortest estimated next CPU burst when the CPU becomes available, and is non-preemptive in this guide. It can reduce average waiting for a known workload, but estimating burst lengths is difficult.
A newly arrived short job still waits for the current burst to finish.
Shortest remaining time (SRT) is preemptive: a new job with less required CPU time than the current job has left can take over. A trace must compare remaining time, not the original burst.
Both shortest-first policies can starve a long job if short jobs keep arriving; ageing can increase waiting jobs' priority. No average metric alone guarantees fairness or deadlines.
Multilevel feedback queues
A multilevel feedback queue (MLFQ) uses several ready queues at different priorities. Higher-priority ready work runs first; jobs at the same level commonly use round robin. New jobs often start high, and using up an allocation can move a CPU-intensive job down.
Behaviour feeds back into scheduling, unlike a fixed multilevel arrangement that never moves jobs between levels.
Exact MLFQ rules vary: quantum sizes, demotion budgets, I/O behaviour and periodic priority boosts must be stated. Boosts/ageing help prevent low-priority starvation. Feedback scheduling can favour interactive work without knowing exact burst lengths, but introduces policy complexity and still has context-switch overhead.
Worked example
Service an input event without losing the current calculation
Assume the interrupted process has PC = 12 and ACC = 9 after its current instruction. An enabled device interrupt is accepted at the instruction boundary.
Save the return address 12, ACC = 9 and any other required registers/status. Set PC to the ISR entry and run the handler, which reads/acknowledges the device.
Restore PC = 12 and ACC = 9 before returning. Without restoring ACC, an ISR's calculation could corrupt the resumed process. The ISR entry address is not the process's saved return address.
Worked example
Four policies on the same arriving jobs
Jobs: A arrives at 0 and needs 7 time units; B arrives at 2 and needs 4; C arrives at 4 and needs 1. One CPU, no I/O or switch overhead. Intervals include their start and exclude their end.
For round robin use quantum 2; arrivals at a slice boundary enter before the expired job is requeued. For SRT, ties keep the current job; otherwise use earlier arrival. SJF/FCFS do not preempt.
SRT runs A for 2 units, then B because 4 < A's remaining 5; C preempts B at time 4 because 1 < B's remaining 2. After C, B finishes before A resumes.
For SRT, B's turnaround is 7 − 2 = 5 and its waiting is 5 − 4 = 1. For round robin, C first starts at 6, so response is 6 − 4 = 2.
Verified schedules and waiting times for A, B, C
Policy
CPU intervals
Completion A/B/C
Waiting A/B/C
FCFS
A 0–7; B 7–11; C 11–12
7 / 11 / 12
0 / 5 / 7
SJF
A 0–7; C 7–8; B 8–12
7 / 12 / 8
0 / 6 / 3
SRT
A 0–2; B 2–4; C 4–5; B 5–7; A 7–12
12 / 7 / 5
5 / 1 / 0
Round robin q=2
A 0–2; B 2–4; A 4–6; C 6–7; B 7–9; A 9–11; A 11–12
12 / 9 / 7
5 / 3 / 2
Worked example
A fully specified feedback-queue trace
A, B and C arrive at time 0 in that order with bursts 6, 3 and 1. There are two queues: high uses quantum 1; low uses quantum 2. Higher-priority ready work preempts low work.
All jobs start high; unfinished jobs consuming their high quantum are demoted; low jobs stay low after their quantum. There is no I/O and no overhead.
High runs A 0–1, B 1–2, C 2–3. C finishes; A and B now wait in low in that order. Low runs A 3–5, B 5–7, A 7–9, A 9–10.
Completion times are A=10, B=7, C=3. Waiting times are completion minus burst: 4, 4, 2. A periodic boost at time 20 would affect no job in this finished workload, but protects waiting low-priority jobs in a continuing workload.
MLFQ state after each high-priority slice
Time
High ready
Low ready
Completed
1
B, C
A (5 remaining)
—
2
C
A (5), B (2)
—
3
Empty
A (5), B (2)
C
Original A-Level practice
5 original questions total 18 marks. Attempt each before opening the independently written indicative marking guidance.
Question 1
4 marks
Explain the four main actions needed when the CPU accepts an interrupt and later resumes the process.
Show solution and marking guidance+
Indicative answer
1 mark: save return PC and sufficient processor context.
1 mark: identify/select the appropriate ISR and transfer control to it.
1 mark: handle and acknowledge the event.
1 mark: restore context and return to the correct continuation point.
Question 2
4 marks
Jobs X and Y both arrive at time 0 in that order, requiring 3 and 2 units. Trace round robin with quantum 1 and no overhead. Calculate Y's waiting time.
Show solution and marking guidance+
Indicative answer
1 mark: X 0–1; Y 1–2.
1 mark: X 2–3; Y 3–4; X 4–5.
1 mark: Y completes at 4, so turnaround is 4.
1 mark: waiting = 4 − 2 = 2 units.
Question 3
4 marks
Job X arrives at 0 with burst 5; Y arrives at 1 with burst 1. Give SJF and SRT timelines and explain the difference.
Show solution and marking guidance+
Indicative answer
1 mark: SJF runs X 0–5, then Y 5–6.
1 mark: SRT runs X 0–1, Y 1–2, X 2–6.
1 mark: SJF does not preempt its current burst.
1 mark: SRT compares Y's 1 with X's remaining 4 and preempts X.
Question 4
4 marks
Explain how MLFQ can favour interactive work and why a periodic priority boost is useful.
Show solution and marking guidance+
Indicative answer
1 mark: new/short-burst jobs can receive high priority and quick CPU access.
1 mark: jobs consuming their allocation can move down, distinguishing CPU-intensive behaviour.
1 mark: continuous high-priority arrivals can otherwise starve low-priority jobs.
1 mark: boosting waiting jobs gives them renewed access; precise results depend on the stated policy.
Question 5
2 marks
A team reduces a quantum from 20 ms to 1 ms. Explain one potential benefit and one cost.
Show solution and marking guidance+
Indicative answer
1 mark: ready interactive processes can get a turn sooner.
1 mark: more context switches consume CPU time and may reduce useful throughput.
Specification and references
This guide addresses OCR H446 1.2.1(c–d). Check your examination year and the complete specification for the assessment scope.
These are independently written explanations and practice questions. CompSciTutoring.co.uk is not affiliated with or endorsed by an examination board. The marking guidance is indicative; always check the syllabus for your examination year.