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Free A-Level Computer Science guide
An adder computes output bits from present inputs. A flip-flop retains a bit of state and changes it according to a clock event. That difference explains their roles in a processor.
Content owner: Michael Print · Written for A-Level learners · Checked against official specifications
A half adder accepts A and B: sum is A XOR B, carry is A AND B. A full adder also accepts carry-in: sum is A XOR B XOR Cin; carry-out is (A AND B) OR ((A XOR B) AND Cin).
For this positive-edge-triggered D-type flip-flop, Q takes the value at D on the rising clock edge and holds its previous state between active edges. The clock staying high does not make Q continuously follow D. Other trigger conventions must be stated by their circuit or question.
OCR H446 · 1.4.3(e), using logic diagrams expressed as named connections and complete truth/state tables. The D-type example is explicitly positive-edge-triggered.
Useful foundations
By the end, you should be able to
Adding 1+1 gives binary 10: sum is the low zero; carry is the high one. The two outputs are separate wires with different meanings.
A half adder has no carry-in. It can serve a least-significant column without an incoming carry, but cannot alone handle every later column. The truth table covers all four input pairs.
| A | B | Sum S | Carry C |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
A full adder accepts A, B and carry-in. Two half adders plus an OR gate produce its sum and carry-out.
For 1+1+1, the total is binary 11: S=1 and Cout=1. Carry-out is one when at least two inputs are one.
Check each truth-table row with total=A+B+Cin, S=total mod 2 and Cout=total div 2. Eight rows exhaust the inputs.
First half adder
A and B produce X=A XOR B and C1=A AND B.
Second half adder
X and Cin produce S=X XOR Cin and C2=X AND Cin.
Combine carries
OR C1 and C2 to produce Cout.
The first intermediate sum feeds the second half adder; both carry outputs feed the final OR.
| A | B | Cin | Sum S | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Each column’s carry-out feeds the next more significant column’s carry-in. In this ripple-carry example, carries take time to propagate before outputs settle. Other adder architectures may compute carries differently.
The final carry can form an extra result bit or flag unsigned overflow if discarded. Signed two’s-complement overflow needs a different test. Never add that final carry back into the least-significant column.
Assume preset/clear are inactive and D is stable around the active edge. A rising edge samples D into Q. Real devices impose setup/hold times; this ideal trace assumes those requirements are met.
During steady clock levels or a falling edge, Q keeps its previous value. A high clock alone does not make Q follow D.
Where provided, the complementary output is NOT Q in normal operation. Several flip-flops sharing a clock can store a register.
An adder is combinational: settled outputs depend on present inputs. A flip-flop is sequential: stored history matters. Its state table therefore needs the clock event and previous Q, not just D.
This guide uses a positive-edge-triggered D-type flip-flop.
| Clock event | D | Q before | Q after |
|---|---|---|---|
| Rising edge | 0 | 0 or 1 | 0 |
| Rising edge | 1 | 0 or 1 | 1 |
| No rising edge | 0 or 1 | 0 | 0 |
| No rising edge | 0 or 1 | 1 | 1 |
Worked example
| Bit | A | B | Cin | S | Cout |
|---|---|---|---|---|---|
| 0 | 1 | 0 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 |
| 2 | 0 | 1 | 1 | 0 | 1 |
| 3 | 1 | 0 | 1 | 0 | 1 |
Worked example
5 original questions total 16 marks. Attempt each before opening the independently written indicative marking guidance.
Give the half-adder outputs when A=B=1 and explain each gate used. [4 marks]
Indicative answer
A full adder receives A=1, B=0 and Cin=1. Calculate S and Cout, then identify why a half adder alone is insufficient. [3 marks]
Indicative answer
For the unsigned addition below, state the five-bit result and explain the effect of retaining only four bits. [3 marks]
Add the unsigned four-bit patterns 1011 and 0110. Start with carry-in zero at the least-significant column and pass each carry-out to the next column. Write the result most significant bit first.
Indicative answer
10001=17 (1). Four retained sum bits are 0001=1 (1); the final carry is lost because 17 exceeds the four-bit unsigned maximum 15 (1).Initially Q=0. Events are rising edge with D=1, D changes to 0 at steady high clock, falling edge with D=0, rising edge with D=0. Give Q after each event. [4 marks]
Indicative answer
Distinguish a full adder from a D-type flip-flop by the dependence of each output. [2 marks]
Indicative answer
This guide addresses OCR H446 1.4.3(e), using logic diagrams expressed as named connections and complete truth/state tables. The D-type example is explicitly positive-edge-triggered.. Check your examination year and the complete specification for the assessment scope.
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