How the fetch–decode–execute cycle works

OCR H446-aligned · register state. A simple processor has PC = 52. Memory location 52 holds JUMP 90. The PC increments during fetch; JUMP n replaces the PC with n during execution. State the MAR value after the PC is copied to it, name the two registers that receive and then hold the instruction, and give the PC value just after fetch and after execution.

AQA 7517-aligned · decode and apply. The MBR receives binary instruction 10110010. Its first four bits are the opcode and its last four the operand. In this invented processor, opcode 1011 loads the immediate operand into the accumulator. Name the bus that brought the instruction from memory and the register that holds it for decoding. Give the opcode, operand and accumulator result in denary.

Cambridge International 9618-aligned · register transfers. Use ← for assignment and Memory[x] for the contents at address x. Initially PC = 73 and Memory[73] = LOAD 5. Complete the simplified fetch transfers below in order, then name the bus carrying the address to memory.

MAR ← ____
PC ← ____
MDR ← Memory[____]
CIR ← ____

OCR H446-aligned · four-mark written answer. A CPU is about to process the next instruction, held at memory address 144. Explain how the address and then the instruction move through the processor during fetch. Distinguish what PC, MAR, MDR and CIR hold, and identify the buses or signal involved. Write a connected explanation.

Cambridge International 9618-aligned · six-mark explanation. A processor receives an interrupt request while executing a program. Explain how it can service the interrupt and then continue the program. Refer to the current instruction, saved state, the interrupt service routine and the next fetch.