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Free A-Level Computer Science guide
A storage circuit's output depends on its previous state as well as its inputs. Declare the active levels and clock edge before deriving its state table.
Content owner: Michael Print · Written for A-Level learners · Checked against official specifications
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Compare an active-high NOR SR latch with an ideal rising-edge JK flip-flop. Apply proposed SR inputs or change the JK clock deliberately; there is no automatic clock.
Two cross-coupled NOR gates form an active-high SR latch. With S=R=0, feedback holds a stable stored bit; S=1,R=0 sets Q; S=0,R=1 resets it. S=R=1 forces both physical outputs low and must not be used as a valid complementary stored state.
For the ideal positive-edge JK model here, J,K=00 holds, 01 resets, 10 sets and 11 toggles at a rising edge. Between active edges Q is retained. Other diagrams/devices may use different clock/input conventions.
Cambridge International 9618 · 15.2 Boolean Algebra and Logic Circuits
Useful foundations
By the end, you should be able to
Cambridge 2027–2029: SR and JK state/circuit reasoning. SR uses active-high cross-coupled NOR; JK uses an ideal rising-edge convention with a drawn D-based next-state implementation. Follow a supplied question's polarity/clock convention instead of assuming it matches this example.
Shared foundations and optional extensions are labelled separately; this page does not claim complete coverage of the qualification.
The top gate gives Q=NOT(R OR Q̅); the lower gate gives Q̅=NOT(S OR Q). Each output is fed back to the other gate's input. The two stable complementary states allow the circuit to retain a bit with S=R=0.
With S=1 and R=0, the lower NOR output becomes 0 and the upper output becomes 1. With R=1 and S=0, the upper output becomes 0 and the lower becomes 1. The stored state persists when the asserted control returns low.
S=R=1 forces both NOR outputs to 0, so they are not complements. Releasing both simultaneously does not specify which stable state wins once physical delays and noise act. A truth table must flag this forbidden condition rather than predict a definite retained bit.
The activity marks the remembered state unknown after that event until an explicit set or reset establishes a known value. An active-low NAND SR circuit has a different table: do not transfer the active-high input rule without re-deriving it.
For the positive-edge model, compare clock before and after the transition. A 0→1 edge uses J and K to calculate a new Q; a 1→0 transition holds. Changing J or K without an active edge changes combinational next-state logic, not the stored output.
With J=K=1, each active edge complements the old Q. A level-sensitive JK implementation can suffer race-around when the enabling pulse permits repeated changes. This ideal edge-triggered exercise models one capture per rising edge and does not simulate physical delays.
The next-state equation is D = J·NOT Q + NOT K·Q. Two AND terms and an OR gate compute D from J,K and output feedback; a positive-edge D flip-flop captures D at the edge. The activity draws the gates, D input, clock symbol and feedback paths.
Substitute J,K=11: D=NOT Q, giving toggle. For 10, D=NOT Q+Q=1; for 01, D=0; for 00, D=Q. This is one logical implementation of the declared JK behaviour, not a claim that every commercial JK device internally uses the drawn D construction.
| J | K | Qnext at rising edge |
|---|---|---|
| 0 | 0 | Qold |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | NOT Qold |
Worked example
4 original questions total 13 marks. Attempt each before opening the independently written indicative marking guidance.
An active-high cross-coupled NOR SR latch starts Q=0. Apply (S,R)=(1,0), then (0,0), then (0,1). State Q after each and explain the middle result.
Indicative answer
For that NOR latch, explain the physical outputs while S=R=1 and why releasing both does not define a predictable complementary state.
Indicative answer
A positive-edge JK flip-flop starts Q=1, clock=0 and J=K=1. Give Q after clock 0→1, then 1→0, then 0→1.
Indicative answer
Use D=J·NOT Q+NOT K·Q to derive the JK next state for J,K=00 and 11. Explain when the D storage element captures the result in this guide.
Indicative answer
This guide addresses Cambridge International 9618 15.2 Boolean Algebra and Logic Circuits. Check your examination year and the complete specification for the assessment scope.
These are independently written explanations and practice questions. CompSciTutoring.co.uk is not affiliated with or endorsed by an examination board. The marking guidance is indicative; always check the syllabus for your examination year.
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